The present invention relates to semiconductor devices and fabrication thereof. In particular, the present invention relates to a method of fabricating a tungsten contact in a semiconductor device and to a semiconductor device incorporating such a tungsten contact.
In the manufacture of the semiconductor devices it is necessary to provide electrically conductive contacts and interconnect layers in order to connect electrically various parts of the device to each other and to external circuitry. Manufacturers of semiconductor devices have appreciated that there is a need further to reduce the size of the devices by, inter alia, reducing the size of the electrical contacts and also the interconnect pitch, without reducing the reliability of the devices and while still keeping the surface planar so that subsequent interconnect layers can be formed. Conventional methods of depositing metal contacts, such as by sputtering, have great difficulty in depositing enough material into the contact holes in order to form reliable electrical connections between the substrate silicon and the metal contact. In addition, the resulting topology is non-planar and can place severe constraints on the complexity of the interconnect layers. These technical problems are particularly encountered in the manufacture of CMOS devices which may require multiple interconnect layers.
A typical conventional CMOS device as shown in FIG. 1 which is a cross-section through a CMOS device. In this known device 2, metal contacts 4 are provided to connect the sources and drains 6,8 of the device 2 to interconnect layers such as metal interconnect layer 10 which defines a bonding pad 12 for connection to external circuitry. The metal contacts 4 are disposed in contact holes 14 defined in the dielectric layers comprised of the field oxide layer 16 the interlevel dielectric layer 18, and the gate oxide layer 22. The method of manufacturing this known device has the limitation that the contact hole 14 must be wide enough and have the correct profile (i.e. it is wider at the top than at the bottom) to allow a limited amount of metal to enter the contact hole 14 thereby to form the contact 4. The obtainable reduction in size of the contact hole is limited by the step coverage capability of conventional sputtering systems. In addition, the metal line width has to be large enough to cover the contact by at least the possible misalignment of the pattern so that the contact is protected during plasma etching of the metal to form the desired patterning of the interconnect layer. Furthermore, by making the contact hole large, any subsequent dielectric layer not only has to be capable of covering the non-planar surface resulting from previous interconnect layers but also has to cover the profile of the metal when it goes down into a contact hole. This requires an involved technique for planarising the next dielectric layer which must be used if further interconnect layers are required. From FIG. 1 it will be seen that in the resultant structure the upper surface of the top dielectric layer 20 is non-planar in the region of the metal contacts 4 and it will also be seen that the width of the metal contacts formed is substantially greater than the width of the corresponding source and drain regions of the semiconductor device which are not covered by the gate and field oxide layers 22,16.
It has been proposed to use tungsten plug technology as a means to enhance semiconductor device planarization and to reduce interconnect pitch design rules. For example, in a paper entitled "Submicron wiring technology with tungsten and planarization" (by C. Kaanta, W. Cote, J. Cronin, K. Holland, P. Lee, and T. Wright, IEDM Conference Proceedings, 9.3, p. 209, 1987) it is disclosed that vercial contact studs can be formed from tungsten. However, it is known that such tungsten plug technology suffers substantial technical problems which are related to the agressive chemistry of the selective tungsten deposition process. In this process, tungsten is deposited by chemical vapour deposition (CVD) and the deposition is auto-catalyzed on silicon or metal surfaces and hence tungsten only deposits in contact holes which have silicon (or tungsten) exposed and not on the dielectric itself. The agressive flourine chemistry can also cause significant damage to the silicon interface and to the source/drain junction. It is well known that particular problems which can occur in the known tungsten plug technology are the phenomenon of tunnelling (which is the formation of microscopic filamentary voids in the silicon beneath the chemically vapour deposited tungsten); encroachment of the tungsten underneath the silicon/dielectric interface; consumption of the silicon by the tungsten thereby lowering the tungsten/silicon interface; and high contact resistances (especially for p+-doped silicon substrates) in the source/drain regions. A paper entitled "Conditions for tunnel formation in LPCVD tungsten films on single crystal silicon" (by R. Blewer, T. Headley and M. Tracy, Tungsten and Other Refractory Metals for VLSI Applications, ed. V. Wells, MRS Pittsburgh Pa., p.115, 1987), a paper entitled "Some recent observations on tunnel defect formation during high temperature post-deposition anneal of CVD W on Si" (by E. Broadbent, D. Sadana, A. Morgan, J. Flanner and R. Ellwanger, Workshop on Tungsten and Other Refractory Metals for VLSI Applications, ed. V. Wells, MRS Pittsburgh Pa., P. 111, 1987) and a paper entitled "Detrimental effects of residual silicon oxides on LPCVD tungsten depositions in shallow junction devices" (by R. Blewer and M. Tracy, Workshop on Tungsten and Other Refractory Metals for VLSI Applications, ed. E. Broadbent, MRS Pittsburgh Pa., P. 235, 1986) all disclose specific problems which can be encountered in the deposition of tungsten on silicon. These articles suggest procedures for reducing the occurrence of the defects in the silicon which can occur on CVD tungsten deposition. For example, it has been suggested carefully to choose the operating regimes in the CVD reactor and to control the gas purity. It has also been noted that pre-cleaning of the silicon surface can reduce the occurrence of defects in the silicon. However, the prior art fails to teach a method of fabricating a tungsten contact in the semiconductor device which can properly control the occurrence of defects such as tunnelling, encroachment of tungsten underneath the silicon/dielectric interface, consumption of the silicon and high contact resistances without compromising the inherent advantages of tungsten plug processing in a viable manufacturing technique.
British Patent Specification No. 2206234 discloses a multi-layer metallisation method for integrated circuits in which a metal sandwich structure of refractory metal/aluminium/refractory metal or alloy is deposited onto a semiconductor substrate. The refractory metal is titanium or an alloy of titanium and tungsten. Portions of the sandwich structure are removed to form interconnect and bonding pad conductors.
British Patent Specification No. 1574582 discloses a method of making a surface barrier connection to a piece of semiconductor material in which a contact metal layer is deposited over an oxide layer on a silicon substrate. The oxide layer has a window exposing the silicon substrate. The contact metal is reacted with the silicon to form a silicide.
British Patent Specification No. 1208030 discloses a semiconductor device having metal layers contacting regions of a silicon substrate. The metal layers extend through holes in an insulating film including a lower insulating layer, a middle glass layer and an upper insulating layer. The glass layer is composed of phosphorus oxide.